Application the operation of vectoring conditions for the synthesis of digital state machines
Abstract
Application the operation of vectoring conditions for the synthesis of digital state machines
Incoming article date: 03.12.2013The article discusses a method for optimizing the synthesis of digital state machines for solving tasks of search patterns with masks on FPGA using automatic models. Standard methods for the synthesis of the FPGA don't optimize digital state machines, but only optimize the placement of logic elements on the chip. The method of vectoring states involve the decomposition the structure of the machine and the combining the variety of states to the vertex-array of states. The states in the vertex-array is controlled by special state machine. This simplifies the addressing to the heights of states of the graph , and optimizes logical structure of machine. The number of states of the digital machine remains unchanged. Vectorization of states is simplifying the synthesis and control of state machine and reduces the number of logical elements.
Keywords: digital state machine, graph of digital state machine, synthesis of digital state machine, FPGA, reconfigurable computing system, pattern search, vectoring states of digital state machine.