The use of a self-timed look up table is explored in order to realize systems of logical functions. The self-timed look up table is modeled in its operational and spacer stages in NI Multisim 10 electronic schematic capture and simulation program by National Instruments Electronics Workbench Group. Efficiency of technical solution is confirmed. Systems of logical functions are described in a principal disjunctive normal form. The problems are set for further research.

Keywords: self-timed curcuit, CMOS transistor, paraphase channel, logical functional system, look up table (LUT), inverter, operating stage, spacer stage, logical element, principal disjunctive normal form (PDNF)